1. Field of the Invention
The present invention relates to a mask pattern correcting method, a mask pattern inspecting method, a photo mask manufacturing method, and a semiconductor device manufacturing method.
2. Description of the Related Art
In recent years, a semiconductor manufacturing technique has been remarkably advanced. Currently, a semiconductor device of a minimum design rule of 0.13 microns is mass-produced. Such downsizing is achieved by remarkable advancement of a fine pattern forming technique such as a mask process technique, a photolithogaphy technique, and an etching technique.
In a generation in which a pattern size is sufficiently large, a shape of a pattern to be formed on a semiconductor wafer is depicted as a design pattern as it is, a mask pattern faithful to the design pattern is generated, the mask pattern is transferred onto a resist film on the wafer by means of a projection optical system, the resist film having the mask pattern thereon is etched to form a resist pattern, and a layer under the resist pattern is etched by using the resist pattern as a mask. With these steps, a pattern substantially corresponding to design pattern can be formed on the wafer. However, with the advancement of pattern downsizing, it has been difficult to faithfully form a pattern in each process. As a result, there occurs a problem that the dimension (finished dimension) of a pattern (finished pattern) finally obtained on the wafer deviates from that of the design pattern. In other words, there occurs a problem that the dimension of the finished pattern deviates from that of the mask pattern. In particular, in a lithography process and an etching process which are the most important to achieve the size-down, the periphery of a pattern to be formed greatly affects dimensional precision of the finished pattern.
There has been reported an optical proximity correction (OPC) technique or a process proximity correction (PPC) technique, in which an assistant pattern is added to the design pattern in order to correct the deviation between the dimension of the finished pattern and that of the mask pattern so that the dimension of the to-be-pattern has a dimension of the desired pattern. These correction techniques become essential techniques in forming a pattern (Japanese Patent Application KOKAI Publication No. 9-319067, page 11 and FIG. 1; Photomask Technology and Management, SPIE Vol. 2322 p 374-336, 1994, “Large Area Optical Proximity Correction using Pattern Based Corrections”, D. M. Newmark, et al.).
In order to achieve high speed circuit operation, in most recent years, downsizing of the gate dimension of a transistor has progressed at higher speed than conventional. Concurrently, an allowable change quantity of the gate dimension of the transistor becomes smaller. If the allowable dimensional change quantity decreases, the following problem occurs in pattern correction processing using the OPC or PPC.
First, it is necessary to downsize a minimum target region for pattern correction, i.e., a unit grid, and concurrently, a mask data volume increases.
In addition, in a rule based OPC, the complication of a correction rule cannot be avoided, and a processing time and an inspection time increases.
Further, in a model based OPC, it becomes important to improve predictive precision of the dimension (finished dimension) of a pattern (finished pattern) on the wafer. Thus, a larger amount of time is required for simulation applied to improve the predictive precision.
These problems also apply to downsizing of a wiring pattern as well as gate downsizing.
Conventionally, a circuit design is made by a simulation using a circuit model under a condition that the gate dimension of the transistor has a dimensional change quantity of a predetermined percentage (for example, ±10%) or a dimensional change quantity of a predetermined length (for example, ±15 nm). Therefore, in order to guarantee a circuit operation of a circuit designed by such a simulation, there is a demand for a dimensional deviation between the gate dimension of the transistor of each circuit unit of the circuit and the design pattern dimension (in other words, mask pattern dimensions) to be included within a dimensional change quantity of the above-described predetermined percentage or a dimensional change quantity of the above-described predetermined length. This dimensional change quantity of the predetermined percentage or dimensional change quantity of the predetermined length is set at an allowable dimensional change quantity of the transistor requested by the severest allowable dimensional change quantity in the transistors in all the circuit units. That is, in order to guarantee the circuit operation, correction must be performed for the transistors in all the circuit units such that the above-described dimensional deviation is included within the severest allowable dimensional change quantity. As a result, a larger amount of time is required for correction, and the correction processing efficiency has been degraded.